This invention relates to a method of managing the memory of a computer system, and a method of reducing the power consumption of a memory, taking particular account of access performance.
An ordinary computer system is provided with hardware and consumes power due to the operation of the hardware. Specifically, hardware means a processing unit (processor), a main memory unit (memory), a secondary storage, and an Input/Output (I/O) device, etc.
When a computer system consumes a large amount of power, the computer system simultaneously generates a lot of heat. Therefore, a cooling installation from which heat is removed must be installed. Due to the high cost of the power consumed by the computer system and the cooling installation is high, when a large-scale computer system is constructed, the system design must take account of the computer performance per power consumption. Hence, a large-scale computer system needs to be designed with a view to reducing power consumption. Since modular devices in the system also have conditions such as the limit of battery capacity, it is necessary to aim to reduce power consumption in these devices too. In a computer system, memory is one such device which consumes power in large amounts. For example, since a large-scale computer system has a very large memory, the proportion of the memory power consumption in the power consumption of the whole computer system is high. The capacity of the memory with which a computer server, a personal computer and modular devices are provided, is also increasing.
The main targets of power consumption are the processor and peripheral devices, and almost no control is performed to reduce the power consumption of the memory. However, from now on, the memory will also be the target of power consumption reduction efforts.
In general, the memory stores commands for the processor to perform calculations, as well as data, etc. Specifically, the processor reads an operating system (OS) or application software from a secondary storage to the memory. The processor reads commands from the memory and performs calculations.
When the processor performs calculations, the memory stores the data required for calculations and the data based on calculations or results.
The memory of a computer system is usually a DRAM (Dynamic Random Access Memory). A DRAM has a transistor and a capacitor, and data is recorded by whether an electric charge is stored in the capacitor. Specifically, when the capacitor stores a charge, “1” is stored, and when the capacitor does not store a charge, “0” is stored. Due to this construction, the charge with which the DRAM is charged by the capacitor is decreased, so in order to maintain the recorded data, refresh must be executed periodically which returns the state of the capacitor to the charged state.
Further, the DRAM can have plural power control management modes, and can usually change to another mode via a memory controller or the like. For example, it can change from a normal mode to a low power mode.
In the low power mode, although power consumption is low compared with the normal mode, the speed with which the processor accesses the memory decreases.
A prior art computer system is known wherein a memory controller has a logical/physical address translation table, and the controller operates the translation table so that the used memory area can be concentrated in any desired memory.
Also, a low power control method is known in which an unused memory list is managed for each memory device by the OS, and memory is allocated memory starting from memory devices which have little unused memory (memory usage is high) (e.g., refer to U.S. Pat. No. 6,954,837). By this process, the memory controller changes over the power mode of an unused memory device to the low power mode, and the power consumption of the memory devices can be reduced.
Another technique is known wherein the power consumption of memory devices is controlled by periodically refreshing only memory devices storing data, and holding the data (e.g., refer to U.S. Pat. No. 6,215,714).
In another technique (e.g., refer to JP 2005-235203 A), instead of performing low power control of the memory, low power control of the processor is executed by detecting, in advance, a command which operates a computing circuit, activating this computing circuit, and after the computation by the computing circuit are completed, inactivating the used computing circuit.